The present invention relates to a blade server apparatus which can form a high-performance server by tightly coupling a plurality of blade server modules, and more particularly, to a blade SMP server apparatus which employs a symmetric multi-processing (SMP) system.
As a known technique of the present invention, a technique for SMP coupling a plurality of blade server modules via a backplane is disclosed in JP-A-2010-009628 (the counterpart US Publication of which is US2011/0016201). A technique for obtaining physical SMP coupling according to a logical SMP arrangement by providing a removable SMP coupling apparatus which mounts blade server modules in place of wiring lines on a backplane is disclosed in JP-A-2010-079467.
In order to design a server apparatus of an SMP arrangement including a plurality of server modules, it is necessary to consider various restrictions. For example, when a server apparatus is designed to simultaneously satisfy a restriction based on a processor architecture and a restriction based on apparatus specifications, the wiring length of the SMP coupling apparatus disclosed in JP-A-2010-079467 becomes much longer, which may, in some cases, deteriorate a signal transmission quality.
This will be explained in detail in connection with a specific example with use of FIGS. 6 to 11.
With respect to the first restriction, connection destinations of processors to be SMP coupled are restricted, in some cases, depending upon a processor architecture to be used. This example is shown in FIG. 6. The number of processors 400 to be SMP coupled in FIG. 6 can be selected from 2, 4 or 8. Each of the processors 400 includes an SMP virtual connecting unit 410 or SMP virtual connector and a processing unit 420 and receives a processor ID from an ID setting circuit 500 outside of the processor. The processors are connected by wiring lines 600. Although only typical ones of the wiring lines are denoted by reference numeral 600 in FIG. 6, all the thick lines wired between the processors are actually denoted by reference numeral 600. The processing unit 420 delivers a packet 700 shown in FIG. 7 to the processor 400. The packet 700 contains a data packet 720 and a destination processor ID 710. The SMP virtual connecting unit 410 instructs the destination packet to use one or ones of the wiring lines 600. At this time, in order to achieve efficient data transmission, the SMP virtual connecting unit 410 has a function of instructing the destination packet to use one or ones of the wiring lines in such a manner that packets are not simultaneously concentrated on a specific wiring line. According to the processor architecture, however, a change in a relationship between the processor ID and the wiring line causes the function not to be lost, which results in that packets are concentrated on a specific wiring line, thus deteriorating the performance. To avoid this and to get the best performance of SMP coupling, there exists, for the processor ID, such a restriction that the wiring lines 600 are required to be connected as shown in FIG. 6.
The word “processor” as used herein refers to a physical single piece as a processor chip, and even a multi-core processor currently as its mainstream is regarded as a single piece.
With respect to the second restriction, the numbering method of the ID numbers may, in some cases, be restricted by the specifications of the server apparatus or the like. This example is shown in FIGS. 8 to 11. FIG. 8 shows an example of arrangement of a server apparatus including 4 of the processors 400 SMP coupled, and FIG. 9 is its mounting example. In the examples, constituent elements denoted by the same reference numeral are the same constituent elements and have the same function. A casing 1 of the server apparatus includes two server modules 10, a backplane 20, a management unit 30, and an SMP coupling device (for four wiring lines) 40. The management unit has an intermodule execution presence/absence instruction acceptor 31 for receiving an instruction of presence or absence of an SMP execution between blades and a trouble information collector 32. The server module 10 has 2 of the processors 400 and a module manager 300, and the module manager 300 has an ID determiner 310 and a trouble detector 320. The module manager 300 informs each processor 400 of a processor ID determined by the ID determiner 310. Meanwhile, the trouble detector 320 receives the processor ID, and indicates a physical processor position, for example, upon occurrence of a trouble so as to have a function of securing maintainability. For this reason, there exists such a restriction that, as an apparatus requirement, the processor IDs is required to be defined to be arranged as #0, #1, #2 and #3 in a physical order sequentially from the left side of FIG. 8 (sequentially from left and sequentially from top in the mounting example of FIG. 9).
Since the processor ID is uniquely determined by the second restriction and a relationship between the ID and connection destination is determined by the first restriction in this way, the connection destinations of substrate wiring lines of the SMP coupling device (for 4 connection) 40 are uniquely determined. When substrate wiring lines are designed so as to fit these restrictions, the wiring length of a longest wiring line 41 becomes nearly equal to a mounting pitch 2 of the server module 10 in FIG. 9.
When the same restrictions are applied to SMP coupling of 8 processors, a problem takes place. FIG. 10 shows an example of arrangement of a server apparatus having 8 of the processors 400 SMP coupled, and FIG. 11 is its mounting example. Constituent elements denoted by the same reference numeral have the same function. Differences between FIGS. 8 and 9 lie in that 4 of the server modules 10 are mounted and an SMP coupling device (for 8 connection) 50 is provided. Explanation of constituent elements having the same construction and function as those in FIGS. 8 and 9 and already explained is omitted In this case, there exists such a restriction that, as an apparatus requirement, processor IDs are required to be defined to be arranged as #0, #1, #2, . . . , and #7 in a physical processor order sequentially from left of FIG. 10 (sequentially from left and sequentially from top in the mounting example of FIG. 11).
Since the processor ID is uniquely determined by the second restriction and the relationship between the ID and connection destination is determined by the first restriction in this way, the connection destinations of substrate wiring lines of the SMP coupling device (for 8 connection) 50 are uniquely determined. When the substrate wiring lines are designed so as to fit these restrictions, the wiring length of a longest wiring line 51 becomes about three times the mounting pitch 2 of the server module 10 in FIG. 11.
When design is made so as to fit these restrictions simultaneously in this way, there may in some cases, occur such a situation that the wiring length of the 8-connection type SMP coupling device becomes 3 times longer than that of the 4-connection type SMP coupling device and a signal transmission quality for the SMP coupling is remarkably deteriorated.
In this connection, even when the substrate is made of an expensive ultra-low-loss material, the expensive substrate can only provide characteristics about 2 times as good as a general-purpose substrate material as its limit. That is, even if such a low-loss material is used, length for wiring can be twice lengthened. Thus, it is insufficient to only employ such an ultra-low-loss material for the substrate of the 8-connection type SMP coupling device 50 and it becomes necessary to employ the ultra-low-loss material even for the substrate of the server module 10. In this case, since the cost of the server module is increased, the employment of the ultra-low-cost material becomes costly for a lower-level arrangement such as a case of no SMP coupling or a case of 4-connection type SMP coupling.
Since the 8-connection type SMP coupling as a maximum arrangement provides a smallest operational margin from the viewpoint of signal transmission quality, most detailed evaluation is required upon its development. On the other hand, in the case of the aforementioned highest-level arrangement, in many cases, much time is required for firmware development and constituent element acquirement, the completion of a test apparatus for evaluation comes last, and evaluation of the highest-level arrangement is, in some cases, started after shipping of the lower-level arrangement. Problems based on the evaluation are picked up most frequently upon evaluation of the smallest-operational margin arrangement For this reason, there is a risk that problem pickup becomes late and thus this leads to a cost increase in a broad sense.